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DD-03296
96-CHANNEL DISCRETE-TO-DIGITAL INTERFACE
FEATURES
DESCRIPTION
The DD-03296 device is a 96-channel discrete-to-digital interface with universal HlRF-isolated inputs that accept 28 V/Open, Open/Gnd and 28 www..com V/Gnd signals. The output is an addressable 8- or 16-bit tri-state port, selectable for channel data, status, bounce, built-in self-test (BIST) and major fault, and is compatible with TTL logic.
APPLICATIONS
The DD-03296 is specifically designed to address built-in self-test autonomy, fault isolation and tolerance. Because of its high reliability and low cost, these features enable the DD03296 to satisfy a variety of interface requirements in aerospace applications, including flight critical, essential, and nonessential functions.
* HIRF Layer * Universal Inputs
28 V/Gnd Open/Gnd 28 V/Open
* Built-in Self-Test * Soft Failure Reporting
Higher MTBUR
* ARINC 429 Output Port
REFERENCE INPUT
DATA 96 BOUNCE 96 REFERENCE INPUT PROCESSOR AND DISCRETE 96 BIT TEST MATRIX INPUTS 96 FAULT 96 ENABLE HI 5 MATRIX SHIFT H/L TEST DISCRETE TRANSFER ENABLE LO 5 ADDRESS 3 3 DISCRETE DATA EN DECODER ARINC DATA EN SEL0 SEL1 SEL2 1 MHZ RESET* DUAL REDUNDANT CLOCK AND CONTROL LOGIC
DISCRETE TRI-STATE DRIVERS
16
DATA BUS
DATA (8/16 BITS)
DISCRETE DATA TRANSFER VERIFIER
TRANSFER FAULT FAULT PROCESSING CIRCUITRY
96
96 TRANSFER FAULT ENABLE* ADDRESS (A5..A0) 8/16 BUS ARINC DATA TRANSFER VERIFIER
FAULT BIT
FAULT*
DISCRETE FAULT
ARINC FAULT
16 ARINC 429 TRI-STATE DRIVERS
DATA BUS
TRI-STATE ENABLES 2 ARINC 429 XMITTER READY 10S CLOCK 80S CLOCK
(TTL) ARINC 429 OUTPUT
ARINC 429 DATA RATE ARINC 429 MESSAGE RATE
DATA READY NOTE: (*) Indicates active low.
FIGURE 1. DD-03296 BLOCK DIAGRAM (c)
1993, 1999 Data Device Corporation
U.S. Patent No. 5526288
TABLE 1. DD-03296 SPECIFICATIONS PARAMETER UNITS MlN TYP MAX ABSOLUTE MAXIMUM RATINGS Supply VoItages (VCC, VDD) V -0.3 5.0 7.0 Reference Inputs V -80 80 80 Discrete Inputs V -80 VDD+0.3 Digital Inputs V -0.3 OPERATING CONDITIONS Supply Voltages (VDD) V 4.5 5.5 DIGITAL INPUTS/OUTPUTS Logic Compatibiliy TTL/ CMOS Digital Inputs sVIH V 2.0 www..com sVIL V 0.8 sVIL (VIN = 0) A -40 -400 Clock Input (See Note 1) Digital Outputs sVOH (lOH = -1ma)
sVOH sV OL
WHAT IS A DISCRETE?
Advisory Circular (FAA), Airworthiness Approval of Traffic Alert and Collision Avoidance Systems (TCAS II) and Mode S Transponders, AC20-131, defines a discrete as "a separate, complete and distinct signal. " In many instances these signals are binary, on or off, 28 V-based signals; they are typically Open/Gnd, 28 V/Open, or 28 V/Gnd with very low bandwidth (DC to 200 Hz). Although the translation of these signals to TTL-levels that are compatible with digital avionics may seem simple, RTCA DO160 power, lightning and high-intensity-radiated-fields (HIRF) are complicating factors. Add to that the desire to have a standardized, addressable, reliable interface and the challenge becomes apparent. Today's systems address the interface requirements with circuits tailored for each interface comprised of R-C input filters, divider networks, diode isolation and comparators. Multichannel interfacing to a processor requires additional logic and latches. The resulting circuit generally lacks any built-in test capability, consumes considerable pc-board real estate (up to one sq. in. per channel) and offers no chip-level redundancy.
MHz V V V
0.99 VDD-0.5 2.4
1.00
1.01
(IOH = -4ma) (lOH = 4ma)
0.4 See FIGURE 4
ANALOG INPUTS POWER SUPPLY REQUIREMENTS (Total VDD, Analog & Digital) IDD (VDD = +5V [Digital Outputs Unloaded]) POWER DISSIPATION PD THERMAL Operating Temperature sType 2 Storage Temp Lead Temperature (Localized, 1 sec. duration) (Body, 2 sec. duration) Junction Temperature jc ca MTBF per Mil-Hbk-217 for Airborne Inhabited Cargo at 64C PHYSICAL CHARACTERISTICS Size Weight
mA
25
45
FUNCTIONAL INTEGRATION
mw 125.0 250.0
C C C C C/W C/W
-40 -65
85 150 280 210 5.0 20.0
Using the aggregated signal definition and functional requirements of industry, ILC Data Device Corporation has developed a discrete interface with universal HIRF-isolated inputs to handle 28V/Open, Open/Gnd and 28V/Gnd signals. Each channel is routed through a HIRF filter and comparator. Its output is a selectable 8- or 16-bit tri-state port, addressable for channel data, status, bounce, built-in self-test and major fault information. This design specifically addresses built-in self-test autonomy, fault isolation and tolerance; moreover, its functional integration results in significant added reliability. A comparative look at MTBF, calculated in accordance with MIL-HBK-217 for airborne inhabited cargo environments at 64C, indicates an order of magnitude improvement (1,400,000 hours vs. 173,000 hours) for a plastic packaged integrated approach vs. a similarly packaged discrete-component implementation. In addition, the real estate used is reduced from as much as 64 to 5 square inches. Additional key DD-03296 features include:
1,400,000 hrs. plastic in (cm) oz (gm) 2.3 x 2.3 (5.84 x 5.84) 0.83 23.5
Note 1: ARINC 429 bit rate is derived from the clock. Refer to ARINC 429 Bit Rate to avoid interference. ARINC 429-14 (January 4, 1993), paragraph 2.4 "Timing Related Elements" contains a "COMMENTARY" section following subparagraph 2.1.4.2 ("Low-Speed Operation") that cautions against using "precisely" 100 kilobits per second.
BOUNCE: Relays and switches, as mechanical devices, have a characteristic `bounce' to their signal transition. It is desirable to mask this bounce by delaying the output digital transition accordingly. This sampling rate of the device can be varied to allow for debounce of relay/switch inputs. In addition, the triplesampling of a given comparator enables a consistent reading of otherwise asynchronous signals. Bounce is an addressable sta-
2
tus that allows the user to detect bouncing or intermittent relays/switches.
sented to the device. The addressed data will be available within 100 nsec. After the data is read, the ENABLE line should be returned to a logic "1" level before the address is changed. All of the data within the device is guaranteed to remain stable for at least 20 sec after the high-to-low transition of the READY signal (See FIGURE 3).
GROUND DIFFERENTIALS: When the reference inputs are connected to the 28V supply, the thresholds are designed to tolerate 3.5V ground differences. REGISTERS: 8- or 16-bit selectable data or status are available via tri-state buffers for interfacing to any system processor. ARINC 429 PORT: A serial ARINC 429 output is available for data-concentrator applications. This enables the transfer of data to other systems with a minimum of wiring and processor loading.
ANALOG INPUTS
ANALOG INPUT CHANNELS: (Pins 161, 162, 1-6, 8-15, 19-26, 29-36, 45-52, 55-62, 66-73, 76-83, 85-92, 95-102, 105-112, 115-122) 600k input resistance, 500s time constant, responsive to Open/Gnd (when configured with appropriate external pull-up), 28V/Open and 28/Gnd input with HIRF/lightning immunity. Refer to FIGURE 4 for detail of the input structure. REFERENCE: Configured for 28V tracking discretes. User adjustable for other reference levels by connecting external resistors between corresponding TRIM and REF inputs.
FIGURE 4 also shows the reference structure. Each set of Ref/Trim inputs are configured by the user for a bank of 32channel inputs. (See FIGURE 4 and TABLE 8)
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HIRF: The device incorporates passive circuitry to isolate the intelligence from both lightning effects and radiated fields as defined in DO-160. This protection is applicable to the discrete inputs, reference inputs and their relationship to each other and to ground. TEST PATTERNS: Internal Test Patterns can be selected to produce alternating "1"s and "0"s to verify that all address and data bits are operational. While these outputs are always available, regardless of READY state, they must be addressed by the user (A5... A0) in accordance with TABLES 3 and 4. DISSIMILAR PATHS: Errors are reported through registers and the ARINC 429 port as cross-checks. INTELLIGENCE: The device's built-in self-test, status reporting scheme and isolation significantly reduces application software requirements. FIGURE 1 illustrates the model DD-03296 functional block diagram. ASYNCHRONOUS SAMPLING: The device takes three samples on each encode because input discrete transition is asynchronous and reports the "majority" state.
REF A, B, C: (Pins 37, 65, and 75) Input to the divider supplying the reference voltage to the "A," "B" and "C" group of 96 input channels. TRIM A, B, C: (Pins 38, 64, and 74) Junction of the first resistor and the rest of the reference "A," "B" and "C" divider.
DIGITAL INPUTS
DEBOUNCE (SEL2...SEL0): (Pins 158-160) The Input Discrete Sampling Rate (Debounce Time) is user-programmable via the three Select lines (SEL2...SEL0) in accordance with TABLE 2. The intent of this function is to mask the bounce of the input dis-
MICROPROCESSOR INTERFACE READ CYCLE TIMING
TABLE 2. DISCRETE SAMPLING RATE
The DD-03296 is configured with either an 8- or 16-bit microprocessor. FIGURE 2 illustrates this interface. The read cycle(s) should be preceded by polling the device's READY bit located within the Status Register. The Status Register can be read at any time regardless of the state of the READY signal (pin 16) from the device. If the READY bit is a logic "1" (this can be easily tested by a branch if negative statement), the address of the desired register, along with the negative true ENABLE signal, should be pre3
SELECT (SEL 2 . . SEL 0) 000 001 010 011 100 101 110 111
SAMPLE RATE 5 msec 10 msec 20 msec 50 msec 100 msec 200 msec 500 msec 1000 msec
+5V
D15..D0 Chan 1..96 A5..A0 Ref A, B, C Sel 2..0
DD-03296
READY Enable 8/16* Bits
CPU
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1 MHz CMOS Clock Osc.
* indicates active low signal
NOTE: 1) If 8/16* Bits pin is tied to +5V, then the DD-03296 is configured for 8-Bit Mode. The following must also be modified: D0 tied to D8 D1 tied to D9 D2 tied to D10 D3 tied to D11 D4 tied to D12 D5 tied to D13 D6 tied to D14 D7 tied to D15 2) If the ARINC 429 option is not used, then pin 153 (429STRBI) MUST be grounded for the "bounce" circuit to operate properly.
FIGURE 2. DD-03296-TO-CPU INTERFACE
Ready
TRA
10 ns Min (See Note 3)
Address TAE Enable* 10 ns Min TEA - 10 ns Min
TED Data
TEDOFF 100 ns Min
50 ns Min
TAVAIL
20 s
Note: 1) TRA = Time Ready Address 2) TAE = Time Address Enable 3) TEA = Time Enable to Address 4) TED = Time Enable Data 5) TEDOFF = Time Enable Off - Data Off 6) TAVAIL = Time Ready* - Data Available 7) (*) Indicates active low. 8) The ready "on-time" = (sample rate - 440 s) Sample rate is programmable via SEL0 - SEL2 (See TABLE 2)
FIGURE 3. READ CYCLE TIMING
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crete appropriate to its characteristic performance. See BOUNCE on page 2.
ENABLE: (Pin 147) The ENABLE line controls the tri-state drivers of the 8- or 16-bit Data Bus outputs. The tri-state Data Bus drivers are enabled when this signal is a logic "0," and are tristated when this signal is a logic "1." ENABLE is a read signal and should only be low during read cycles. 8 /16 BITS: (Pin 104) A logic "0" selects the 16-bit data bus output and a logic "1" selects the 8-bit data bus output. ADDRESS LINES (A5...A0): (Pins 139, 140 and 143-146) The six address lines (A5... A0, where A0 is the LSB) provide for the www..com selection of the desired 8- or 16-bit Data Bus information in accordance with TABLE 3 and TABLE 4 (Word/Byte Modes). CLOCK (1MHZ CLK): (Pin 28) The user must supply a 1 MHz clock whose stability is of no importance except to the serial bit rate of the ARINC 429 port (see Note 1 of TABLE 1). The clock is brought into the internal ASIC at two widely separated points designated as CLOCK_A (primary) and CLOCK_B (secondary) path.
The primary clock path will be selected and drive the device unless a primary clock path fault is detected, in which case the operation of the device will get switched over to the secondary clock path. Both clock paths are continually monitored for status and this information is available as separate bits in the Status Register.
FACTORY TEST INPUTS: (Pins 39, 40, 149 and 150) The TMUX, TMODE, FMUX and FMODE input signals are used for factory testing and should be tied to logic "1" for the device to operate properly. RESET: (Pin 41) The RESET signal is used to reset the device during factory testing. It may be connected to an external RC network to provide a Power-on-Reset for the device. Under normal operating conditions this pin should be a no-connect. If there is some reason to reset the device from external circuitry this pin can be momentarily pulled to logic "0" through an open collector device. Do not hard wire this pin to +5V or ground.
OUTPUTS
DATA (D15...D0): (Pins 123-138) 8-bit byte or 16-bit byte word information is available on the Data Bus depending on the logic state of the Bus Select line as described above.
In the Byte mode the upper and lower bytes are enabled separately so that bit 0 can be hard-wired to bit 8, bit 1 to bit 9 etc., thereby providing an 8-bit data bus. It is important that the 8-bit mode be selected if these data bits are wired together or corrupted data will result. The available data can be found under the Address Lines section found on page 5.
FAULT: (Pin 148) The FAULT flag was designed to serve as an interrupt to the microprocessor when a HARD error has been detected within the device (See Note 2 of TABLES 3 and 4). If this
600k CHANNEL N INPUT COMPARATOR 60k .01 f
+ OUTPUT TO LOGIC TO OTHER COMPARATORS
93.3k REF A
1.0k
5.72k TRIM A
.1 f
IDENTICAL REFERENCE STRUCTURE FOR REF B AND REF C
FIGURE 4. DD-03296 INPUT STRUCTURE
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TABLE 3. WORD MODE (16-BIT BUS) ADDRESS (A5 . . A0) 00 000X 00 001X 00 010X 00 011X 00 100X 00 101X 00 110X 00 111X 01 000X 01 001X 01 010X www..com 01 011X 01 100X 01 101X 01 110X 01 111X 10 000X 10 001X 10 010X 10 011X 10 100X 10 101X 10 110X 10 111X 11 000X 11 001X 11 010X 11 011X 11 111X DATA (D15..D0) BOUNCE CH_16 CH_01 BOUNCE CH_32 CH_17 BOUNCE CH_48 CH_33 BOUNCE CH_64 CH_49 BOUNCE CH_80 CH_65 BOUNCE CH_96 CH_81 FAULT CH_16..CH_01 FAULT CH_32..CH_17 FAULT CH_48..CH_33 FAULT CH_64..CH_49 TEST PATTERN 0's and 1's FAULT CH_80..CH_65 FAULT CH_96..CH_81 DATA CH_16..CH_01 DATA CH_32..CH_17 DATA CH_48..CH_33 DATA CH_64..CH_49 DATA CH_80..CH_65 DATA CH_96..CH_81 NOT USED STATUS REGISTER TEST PATTERN 1's and 0`s FACTORY TEST WORD 1 FACTORY TEST WORD 2 FACTORY TEST WORD 3 FACTORY TEST WORD 4 NOT USED : NOT USED
NOTES FOR TABLES 3 AND 4. Note 1: A true BOUNCE bit indicates that the input signal of the associated channel changed in an alternating fashion, i.e., OFF-ON-OFF or ONOFF-ON in three successive samples at the selected sampled rate. Note 2: A FAULT bit that is true indicates that the associated channel has a major problem and that the associated data should not be believed. A FAULT indication is a HARD FAULT condition indicating that the Built-In-Test has failed. Note 3: A DATA bit indicates the input discrete state for the associated channel over the last two data samples taken. Note 4: The two available TEST PATTERNS contain an alternating string of 1's and 0's, and 0's and 1's, which can be used to verify that all of the data bits are operational (i.e., there are no stuck bits). The two test patterns have been located at addresses of alternating address bits so that the address decoder bits are tested at the same time.
TABLE ADDRESS (A5. . A0) 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 10 0000 10 0001 10 0010 10 0011 10 0100 10 0101 10 0110 10 0111 10 1000 10 1001 10 1010 10 1011 10 1100 10 1101 10 1110 10 1111 11 0000 11 0001 11 0010 11 0011 11 0100 11 0111 11 1111
4. BYTE MODE (8-BIT BUS) DATA (D7..D0) BOUNCE CH_08 CH_01 BOUNCE CH_16 CH_09 BOUNCE CH_24 CH_17 BOUNCE CH_32 CH_25 BOUNCE CH_40 CH_33 BOUNCE CH_48 CH_41 BOUNCE CH_56 CH_49 BOUNCE CH_64 CH_57 BOUNCE CH_73 CH_65 BOUNCE CH_80 CH_74 BOUNCE CH_88 CH_81 BOUNCE CH_96 CH_89 FAULT CH_08 CH_01 FAULT CH_16 CH_09 FAULT CH_24 CH_17 FAULT CH_32 CH_25 FAULT CH_40 CH_33 FAULT CH_48 CH_41 FAULT CH_56 CH_49 FAULT CH_64 CH_57 TEST PATTERN 0's and 1`s TEST PATTERN 0's and 1`s FAULT CH_73 CH_65 FAULT CH_80 CH_74 FAULT CH_88 CH_81 FAULT CH_96 CH_89 DATA CH_08..CH_01 DATA CH_16..CH_09 DATA CH_24..CH_17 DATA CH_32..CH_25 DATA CH_40..CH_33 DATA CH_48..CH_41 DATA CH_56..CH_49 DATA CH_64..CH_57 DATA CH_72..CH_65 DATA CH_80..CH_73 DATA CH_88..CH_81 DATA CH_96..CH_89 NOT USED NOT USED STATUS REGISTER LO STATUS REGISTER HI TEST PATTERN 1's and 0's TEST PATTERN 1's and 0's TEST WORD 1 LO TEST WORD 1 HI TEST WORD 2 LO TEST WORD 2 HI TEST WORD 3 LO TEST WORD 3 HI TEST WORD 4 LO TEST WORD 4 HI NOT USED : NOT USED
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signal is asserted (logic "0") the Status Register should be read to determine the nature of the fault. Thereafter more detailed information can be found in the associated addressable registers. The Fault Flag will remain at a logic "0" for as long as the fault condition persists. FIGURE 5 illustrates the fault logic tree. Note: Depending on the exact nature of the fault, the Fault Flag may return to logic "0" during the Built-In-Test interval (when the READY signal is at logic "0") if there is a persistent fault condition. Fault Conditions: FAULT is logic "0" for any of the following fault conditions. The reason for the fault can be obtained from the status register www..com which is accessible regardless of READY state. TABLE 5 shows the contents of the status register. A definition of each bit is as follows: BIT FAULT: A logic "1" for this bit indicates that one of the channels has failed the Built-In-Test sequence; this bit sequence is performed prior to every input sample taken. These signals are reset at the start of each Built-In-Test sequence, and will be set if any of the tests in the sequence fail. DISCRETE FAULT: A logic "1" for this bit indicates that one of the channels detected that the discrete input data word did not transfer to the data bus output properly when it was read. If a HARD fault was detected the offending channel can be determined by reading the associated FAULT data registers. If it was generated by a transfer error the DISCRETE TRANSFER FAULT bit in this status register will be set to logic "1." ARINC FAULT: A logic "1" for this bit indicates that one of the channels detected a HARD failure during Built-In-Test sequence, or that the discrete input data word did not transfer to the ARINC transmitter section properly. If a HARD fault was detected the offending channel can be determined by reading the associated FAULT data registers. If it was generated by a transfer error then no FAULT bits in the status register will be set to logic "1." ARINC READY: A logic "0" for this bit indicates that an ARINC transmission is currently in progress. A logic "1" indicates that no ARINC transmission is in progress. CLOCK_A FAULT: A logic "1" for this bit indicates that the primary 1 MHz clock circuitry is defective and that the device is running off the secondary 1 MHz clock. CLOCK_B FAULT: A logic "1" for this bit indicates that the secondary 1 MHz clock currently is defective and and cannot be used as a backup.
NO CLOCK: A logic "1" for this bit indicates that there is no 1 MHz clock being supplied to the device, or that both have failed. DISCRETE TRANSFER FAULT: A logic "1" for this bit indicates that the discrete data word(s) did not transfer properly during the associated microprocessor read cycle (i.e., the word present on the data bus did not agree with internal data). The most likely cause of this type of fault condition is a collision on the data bus during the read cycle. Note: This condition is only monitored for the discrete data words, not for all of the available data.
CLKTST: (Pin 157) This signal is used for factory testing and should not be connected to any external circuitry or normal operation of the device could be affected. Specifically, this signal is a low drive internal test point connected to the primary clock signal. Grounding this signal forces the device to switch to the secondary internal clock. READY: (Pin 16) A logic "1" for this bit indicates that all of the available data is stable and can be read. A logic "0" indicates that the device is in Built-In-Test mode, or taking a sample of discrete input data lines.
The signal should be polled directly by reading the status word prior to performing any read cycles. The internal data is guaranteed to be stable for 20 sec after the logic "1" to logic "0" transition (READY to NOT READY) of this signal. Therefore, it should not be necessary to repoll the signal after the read.
BIT 00 (LSB) 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 (MSB)
TABLE 5. STATUS WORD BIT MAP SIGNAL BIT FAULT DISCRETE FAULT ARINC FAULT ARINC READY CLOCK_A FAULT CLOCK_B FAULT NO CLOCK DISCRETE TRANSFER FAULT LOGIC LOW (HIGH BYTE) LOGIC LOW LOGIC LOW LOGIC LOW LOGIC LOW LOGIC LOW LOGIC LOW READY
Note: All bits available regardless of ready-state.
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NO CLOCK DISCRETE TRANSFER FAULT (STATUS REG)
(STATUS REG)
MATRIX CIRCUIT FAULT
96 1 2 3 1 2 3
R S
Q
DISCRETE FAULT (STATUS REG)
BOUNCE
96
BIT FAIL
1 2
3
FAULT* (Pin 148)
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96
(STATUS REG) CLOCK A MISSING CLOCK B MISSING
1 2 3 1 2 3
R S
Q
BIT FAULT (STATUS REG)
(STATUS REG)
READ STATUS CLEAR STROBE
Note: (*) indicates active low.
FIGURE 5. FAULT LOGIC TREE
ARINC 429 PORT
This port enables the transmission of discrete data via a serial ARINC 429 (CMOS levels) output simultaneously with the 8/16bit Bus output. The following features and pins apply: 429 serial port and is not connected to a local microprocessor. When the device is being used in this specific configuration the associated 429 Strobe Out should be connected to this pin. In other cases this pin must be grounded. Related Information: Because the BOUNCE data is momentarilly latched within the device, this information is normally reset by a READ to the associated BOUNCE data words. In the instances when there is no microprocessor, and therefore no READS to the BOUNCE data, this connection provides a mechanism to reset the source of the BOUNCE information (just after it is transferred to the ARINC transmitter section) at the start of each ARINC message.
ARINC 429 DATA RATE (429DRATE): (Pin 156) A logic "1" (or a no-connect) for this input selects the ARINC 429 Low-Speed data rate of 12.5 kHz. A logic "0" selects the High-Speed data rate of 100 kHz. ARINC 429 MESSAGE RATE (429MRATE): (Pin 155) The message rate of the ARINC 429 output is selectable at either a fixed 100 ms rate or at the selected sampling rate of the input discretes. A logic "1" selects the input sampling rate as the message rate, and a logic "0" selects the fixed 100 ms message rate.
Note: If the Low-Speed ARINC 429 bit rate is selected (12.5 kHz) an entire ARINC message will take about 52 ms to complete. Therefore, input discrete sampling rates of 5 msec, 10 msec, and 20 msec cannot be utilized or the ARINC message will be truncated unless the fixed 100 ms message rate is selected.
429 STROBE OUT (429STRBO): (Pin 154) This signal is used in conjunction with the "429 Strobe In" described above. It is a 500 ns positive pulse which occurs at the start of each 429 message. For further information concerning the use of this signal, see the 429 STROBE IN section. ARINC_LO AND ARINC_HI: (Pin 151 and 152) These two signals comprise the ARINC 429 serial output transmission. Both are TTL-compatible signals where the ARINC_LO signal contains the logic "0" serial transmission and the ARINC_HI signal
429 STROBE IN (429STRBI): (Pin 153) This pin is utilized in the special case where the device is being used as a remote ARINC
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TABLE 6. ARINC BIT DESCRIPTION LABEL REVERSED OCTAL P A R ARINC 429 BITS FAULT 16..1 FAULT 32..17 FAULT 48..33 FAULT 64..49 FAULT 80..65 FAULT 96..81 BOUNCE 16..1 www..com BOUNCE 32..17 BOUNCE 48..33 BOUNCE 64..49 TEST 5'S TEST A'S BOUNCE 80..65 BOUNCE 96..81 DATA 16..1 DATA 32..17 DATA 48..33 DATA 64..49 DATA 80..65 DATA 96..81 SSM M S B 16 BIT DATA L S B F C SDI L S B 8 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 7 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 6 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 5 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M S B 1 0 001 0 002 0 003 0 004 0 005 0 006 0 007 0 010 0 011 0 012 0 013 0 014 0 015 0 016 0 017 0 020 0 021 0 022 0 023 0 024
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 P P P P P P P P P P P P P P P P P P P P A A A A A A A A A A 1 1 A A A A A A A A BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 DDE DDE DDE DDE DDE DDE DDE DDE DDE DDE 0 1 1E 0E F F F F F F F F F F F F F F F F F F F F CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH CGH
BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD BDDDDDDDDDDDDDD
DDE DDE DDE DDE DDE DDE DDE DDE
Notes: A B = 0 0 If there are no major faults. A B = 1 1 If major faults exist (data is bad). C = 0 When 429 data rate is 100 kbps; C = 1 When data rate is 12.5 kbps. D = Data bit. F = 1 If the discrete interface output has any major faults (429 data may still be good). P = ARINC 429 parity bit. E = 1 If there is a bit fault G H = The value of these two locations will track channel 1 and 2 or can be hard-wired (via channel 1 and 2) to determine which R0D3 the 429 word came from. The 20 words are transmitted in order shown from top to bottom.
contains the logic "1" serial transmission. These two signals must be connected to a 429 Line Driver (DD-03182) to obtain a single-ended ARINC 429 transmition signal. FIGURE 7 illustrates this interface. The content and word order of the ARINC 429 transmission is shown in TABLE 6. As noted, these features are only guaranteed and tested if the ARINC 429 option is selected. In addition, the clock frequency (1 MHz) must be selected carefully so as not to interfere with other avionic communications as detailed in ARINC 429. The ARINC 429 option bit rate is derived from the (1 MHz) clock. Refer to ARINC 429 Bit Rate to avoid interference. ARINC 429-14 (January 4, 1993), paragraph 2.4 "Timing Related Elements" contains a "COMMENTARY" section following subparagraph 2.1.4.2 ("Low-Speed Operation") that cautions against using "precisely" 100 kilobits per second.
429 LINE-DRIVER
If you use the 429 option for the DD-03296, you can use a linedriver chip to transmit the data on the serial data bus. DDC has such a device, the DD-03182, which will support ARINC 429, 571, and 575 bus standards (see TABLE 7), and is available in four package types as indicated in FIGURES 8, 9 and 10. The serial data is presented on DATA (A) and DATA (B) inputs in a dual-rail format. The driver is enabled by the SYNC and CLOCK inputs. The output voltage level is programmed by the VREF input and is normally tied to +5 VDC, along with V1, to produce output levels of +5 V, 0 V and -5 V on each output for 10V differential outputs (see FIGURE6). The output resistance is 75 Ohms 20%; 37.5 Ohms on each output. The outputs are fused for fail-safe protection against shorts to aircraft power. The output slew rate is controlled by external timing capacitors on CA and CB. Typical values are 75 pF for 100 kHz data and 500 pF for 12.5 kHz data. 9
A B
IN
IN
+V REF A -V
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OUT REF
0V
+V B -V
REF OUT REF 0V
Note: The output slew rates are controlled by timing capacitors CA and CB. They are charged by +/- 200 uA (nominal). Slew rate (SR) is calculated by SR = 200/C (V/us) where C is in pF.
FIGURE 6. ARINC 429 WAVEFORM
+5V
* 429DRATE 429MRATE
+15V -15V
Chan 1..96 Ref A, B, C Sel 2..0
DD-03296
ARINC LO ARINC HI 429STRBO 429STRBI
DD-03182 429 LINEDRIVER
ARINC
1 MHz Clock Osc.
NOTE: 1) 429 MRATE and DRATE can either be tied to gnd or +5V (Refer to Page 8).
2) If the ARINC 429 option is not used, then pin 153 (429STRBI) MUST be grounded for the "bounce" circuit to operate properly.
FIGURE 7. DD-03296 TO ARINC 429 INTERFACE
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DD-03182 LINE DRIVER PIN DESCRIPTIONS
See FIGURES 8, 9 and 10 for reference. VREF (Input) - the voltage on VREF sets the output voltage levels on AOUT and BOUT. The output logic level swings between +VREF volts, 0 volts and -VREF volts. N/C - No Connection SYNC (Input) - Logic 0 will force outputs to NULL or MARK state. Logic 1 enables data transmission. CLOCK (Input) - Logic 0 will force outputs to NULL or MARK state. Logic 1 enables data transmission.
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TABLE 7. DD-03182 LINE DRIVER SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUM RATINGS VOLTAGE BETWEEN PINS +V and -V V1 and GND VREF and GND POWER SUPPLY REQUIREMENTS +V -V V1 VREF (for ARINC 429) VREF (for other applications) THERMAL Operating Ambient Temperature Ceramic Plastic Storage Temperature Lead Temperature (localized 10 sec duration) Thermal Resistance: Junction to Ambient ja DD-03182DC DD-03182PP DD-03182GP DD-03182VP Junction Temperature UNITS MIN TYP MAX
V V V
40 7 6
DATA(A)/DATA(B) (Inputs) - Signals containing the serial data CA/CB (Analog) - External timing capacitors are tied from these points to ground to establish the output signal slew rate. Typically, CA = CB = 75 pF for 100 kHz data and CA = CB = 500 pF for 12.5 kHz data. AOUT/BOUT (Outputs) - Line driver outputs which are connected to the aircraft serial data bus. -V (Input) - Negative supply input (-15 VDC nominal). GND - Ground. +V (Input) - Positive supply input (+15 VDC nominal). V1 (Input) - Logic supply input (+5 VDC nominal).
VDC VDC VDC VDC VDC
11.4 -11.4 4.75 4.75 0
15 -15 5 5
16.5 -16.5 5.25 5.25
C C C C
-55 -40 -65
+125 +85 +150 +300
C/W C/W C/W C/W C
75 95 115 130 175
Note: Refer to DD-03182 data sheet for more information.
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TOP VIEW
1 N/C SYNC DATA(A) CA
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TOP VIEW
14 13 12 11 10 9 8 V1 CLOCK DATA(B) CB B OUT +V GND N/C SYNC DATA(A) CA A OUT -V GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V1 N/C CLOCK DATA(B) CB B OUT N/C +V
2 3 4 5 6 7
A OUT -V
FIGURE 8. DD-03182VP PIN CONFIGURATION
FIGURE 9. DD-03182DC AND GP PIN CONFIGURATION
TOP VIEW
S Y N C
4
G N D
3
N / C
2
V
R E F
V
1
N / C
27
N / C
26
1
28
N/C DATA (A)
5
25
CLOCK N/C DATA (B)
6
24
N/C N/C CA N/C N/C
7
23
8
DD-03182PP PLCC
22
CB N/C
9
21
10
20
N/C
11
19
N/C
12
13
14
15
16
17
18
N / C
A
O U T
-v
G N D
+v
B
O U T
N / C
FIGURE 10. DD-03182PP PIN CONFIGURATION
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DIMENSIONS ARE IN INCHES (mm)
LEAD #1 0.785 MAX (19.939) 0.025 RAD (0.635) 0.291 MAX (7.391)
0.050 MAX (1.270)
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0.160 MAX (4.064)
0.060 0.005 (1.524 0.127) 0.125 MIN (3.175) 0 - 10 deg.
0.290 - 0.320 (7.39 - 8.13)
0.020 - 0.070 (0.508 - 1.778) 0.100 0.010 (2.540 0.254) 0.018 0.002 (0.457 0.051) 0.385 0.025 (9.779 0.635)
0.008 - 0.012 (0.203 - 0.305)
FIGURE 11. DD-03182DC 16-PIN CERAMIC DIP (JE) MECHANICAL OUTLINE
PIN 1
DIMENSIONS ARE IN INCHES (mm) LEAD COPLANARITY 0.004 MAX
0.026 MIN 0.032 MAX (0.66 MIN 0.81 MAX) 0.397 MIN 0.413 MAX (10.08 MIN 10.49 MAX) 0.092 MIN 0.094 MAX (2.34 MIN 2.39 MAX)
0.291 MIN 0.300 MAX (7.39 MIN 7.62 MAX)
0.007 MIN 0.013 MAX (0.18 MIN 0.33 MAX)
0.047MIN 0.053 MAX (1.19 MIN 1.35 MAX) 0.014 MIN 0.019 MAX (0.36 MIN 0.48 MAX) 0.003 MIN 0.012 MAX (0.076 MIN 0.30 MAX) 0.393 MIN 0.420 MAX (9.98 MIN 10.67 MAX)
0.015 MIN 0.050 MAX (0.38 MIN 1.27 MAX)
FIGURE 12. DD-03182GP 16-PIN SURFACE MOUNT (SOIC) MECHANICAL OUTLINE
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PIN 1
DIMENSIONS ARE IN INCHES (mm)
0.181 - 0.205 (4.597 - 5.207) 0.150 - 0.158 (3.810 - 4.013) 0.228 - 0.244 (5.791 - 6.198)
0.018 - 0.022 (0.457 - 0.559)
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0.336 - 0.344 (8.534 - 8.737)
0.053 - 0.069 (1.346 - 1.753)
3 - 6
0.007 - 0.009 (0.178 - 0.229)
0.05 (1.270) BSC 0.014 - 0.018 (0.356 - 0.457) 0.004 - 0.008 (0.102 - 0.203)
FIGURE 13. DD-03182VP 14-PIN SURFACE MOUNT (SOIC) MECHANICAL OUTLINE
0.005
0.490 [12.45)]
0.002
ORIENTATION MARK DENOTES PIN 1 0.175 [4.45]
0.454 [11.53]
0.100 [2.54] 0.018 [0.46] MIN
1
0.002
0.002
0.490 [12.45]
0.454 [11.53]
6 EQ. SP @ 0.050 = 0.300 (TOL NONCUM) (TYP) 1
0.020
0.410 [10.41]
0.050 [1.27] (TYP)
0.029 [0.74] (TYP)
0.020 [0.51] MIN
Notes: 1. LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN 0.010.
2. DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS].
FIGURE 14. DD-03182PP 28-PIN (PLCC) MECHANICAL OUTLINE
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TABLE 8. DD-03296 PIN FUNCTIONS PIN NUMBER
1 2 3 4 5 6 7 8 9 10 11 12 13
FUNCTION
CH_03 CH_04 CH_05 CH_06 CH_07 CH_08 N/C CH_09 CH_10 CH_11 CH_12 CH_13 CH_14 CH_15 CH_16 READY N/C N/C CH_17 CH_18 CH_19 CH_20 CH_21 CH_22 CH_23 CH_24 VDD (ANALOG) 1 MHz CLK CH_25 CH_26 CH_27 CH_28 CH_29 CH_30 CH_31 CH_32 REF: CH_ 01-32 TRIM: CH_ 01-32 TMODE TMUX RESET N/C N/C N/C CH_33 CH_34 CH_35 CH_36 CH_37 CH_38 CH_39 CH_40 N/C N/C
PIN NUMBER
55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 (Note 1) 104 105 106 107 108
FUNCTION
CH_41 CH_42 CH_43 CH_44 CH_45 CH_46 CH_47 CH_48 N/C TRIM: CH_ 65-96 REF: CH_65-96 CH_49 CH_50 CH_51 CH_52 CH_53 CH_54 CH_55 CH_56 TRIM: CH_33-64 REF: CH_33-64 CH_57 CH_58 CH_59 CH_60 CH_61 CH_62 CH_63 CH_64 N/C CH_96 CH_95 CH_94 CH_93 CH_92 CH_91 CH_90 CH_89 N/C N/C CH_88 CH_87 CH_86 CH_85 CH_84 CH_83 CH_82 CH_81 GND (ANALOG) 8/16 BITS CH_80 CH_79 CH_78 CH_77
PIN NUMBER
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 (Note 1) 142 (Note 1) 143 144 145 146 147 148 149 (Note 2) 150 (Note 2) 151 152 153 (Note 4) 154 155 156 157 (Note 3) 158 159 160 161 162
FUNCTION
CH_76 CH_75 CH_74 CH_73 N/C N/C CH_72 CH_71 CH_70 CH_69 CH_68 CH_67 CH_66 CH_65 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 A05 A04 GND (DIGITAL) VDD (DIGITAL) A03 A02 A01 A00 ENABLE FAULT FMUX FMODE ARINC_LO ARINC_HI 429_STRBI 429_STRBO 429_MRATE 429_DRATE CLKTEST SEL0 SEL1 SEL2 CH_01 CH_02
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14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Note 1) 28 29 30 31 32 33 34 35 36 37 38 39 (Note 2) 40 (Note 2) 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Notes for TABLE 8:
1. VDD (Digital) and VDD (Analog) MUST be connected to the same power source; GND (Digital) and GND (Analog) MUST be connected to the same GND potential. 2. These signals should be tied to +5V. 3. DO NOT CONNECT 4. This pin must be grounded if 429 ARINC is not implemented.
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+0.010
2.300 -0.000 (58.42)
0.010
0.125 (3.18)
41 EQ. SP @ 0.050 = 2.050 (1.27 = 52.07) [TOL NON CUM]
162 121 120
INDEX MARK DENOTES PIN 1
1
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41 EQ. SP @ 0.050 = 2.050 (1.27 = 52.07) [TOL NON CUM]
+0.010
35 EQ. SP @ 0.050 = 1.750 (1.27 = 44.45) [TOL NON CUM]
2.300 -0.000 (58.42)
0.018 (0.46) [TYP]
0.050 (1.27) [TYP]
85
0.010
0.425 (10.80)
42 43
0.010
84
0.125 (3.18)
DETAIL "A" NTS
COMPONENT ENVELOPE
0.250 MAX (6.35)
0.025 0.005 (0.635)
0.015 (0.38) [TYP]
0.020 (0.51) R MAX [TYP]
0.002
0.010 (0.25) [TYP] 0.065 (1.65) [TYP]
0.040 (1.02)
0.185 .010 (4.69)
2.675 0.010 [TYP] (67.95)
0.075 (1.91) [TYP] 0.185 (4.70) [REF]
SEE DETAIL "A"
Note: Dimensions are in inches (millimeters).
FIGURE 15. DD-03296 MECHANICAL OUTLINE
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ORDERING INFORMATION DD-03296FP-XX0 Screening: 0 = Standard DDC procedures Temperature Range: 2 = -40 to +85C ASIC Package Type: P = Plastic Package Style: F = Surface Mount
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OPTIONAL HARDWARE
DD-03182XX-XXXX - ARINC 429 Line Driver T = Tape and Reel (GP and VP only) Options: 0 = With resistors and fuses 1 = With resistors, no fuses* Screening: 0 = Standard DDC Procedures 2 = Burn-in (ceramic only) Temperature Range: 1 = -55 to +125C (ceramic only) 2 = -40 to +85C 9 = -55 to +85C (GP package only) Package Style/Type: DC = 16-pin ceramic DIP GP = 16-pin plastic SOIC PP = 28-pin plastic PLCC VP = 14-Pin plastic SOIC *VP version only.
OTHER APPLICABLE DOCUMENTS
RTCA/DO-160D: Environmental Conditions and Test Procedure for Airborne Equipment
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The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7402 Headquarters - Tel: (631) 567-5600 ext. 7402, Fax: (631) 567-7358 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com
ILC DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976
C-06/98-1M
PRINTED IN THE U.S.A.
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